PREFACE This was presented as an invited paper by M. G. Buehler at the Large-Scale Integration (LSI) Process Technology/Semiconductor Preparation and Characterization Session of the Electrochemical Society Meeting in Toronto, Canada on May 14, 1975. An abstract was published in Extended Abstracts, The Electrochemical Society, Vol. 75-1, 403-404 (1975). The work was conducted as part of the Semiconductor Technology In the semiconductor industry it is common practice to design photomasks in English units. The photomasks used in this study were laid out in English units. The equivalent metric unit is given in parentheses and in some cases rounded off to an appropriate number of significant figures. PLANAR TEST STRUCTURES FOR CHARACTERIZING IMPURITIES IN SILICON by M. G. Buehler, J. M. David, R. L. Mattis, W. E. Phillips, and W. R. Thurber Abstract: Various test structures such as sheet Key Words: MOS capacitors; p-n junctions; resis- 1. INTRODUCTION The kinds of planar test structures discussed here consist of sheet resistors, p-n junctions, and MOS capacitors. These structures were used to determine the sheet resistance of diffused layers, the dopant density and resistivity of bulk collector regions, and the identity of defect centers such as gold. The discussion of diffused layers involves the intercomparison, design, and over-etch of sheet resistors. Simple and economical sheet resistance measurements are shown to lead to values for the width of diffused layers. For device design, it is essential to have a correct resistivity versus dopant density relation, and various structures were designed to update this relation in both n- and p-type silicon. Dopant density values were obtained from gated diodes and MOS capacitors, and resistivity values were obtained from collector four-probe resistors fabricated on wafers with a variety of resistivities. The measured values were combined into a resistivity versus dopant density plot and compared with existing relations. For p-type silicon the traditionally used Irvin curve [1] differs significantly from the more recent Wagner curve [2] which also differs from our experimental data. The important device characteristics, lifetime and leakage current, are degraded by defect centers such as gold. This defect center was studied in n-type MOS capacitors and in both pn and ntp junctions. From thermally stimulated current measurements, the current response is very different for gold doped p*n as compared with ntp junctions. But the responses of gold doped n-type MOS capacitors and gold doped pn junctions are essentially the same. These thermally stimulated current responses can lead to rapid identification of gold contamination in silicon devices. The thrust of this work emphasizes well-designed and miniaturized test structures and the development of the associated mathematical models. Once developed, these test structures could become part of a process control test pattern. The test structures used in this study are included in test pattern NBS-3 [3]. This pattern, which is shown in figure 1, was designed primarily for use in the evaluation of the resistivity versus dopant density relation. The overall size of the pattern is 200 mil (5.08 mm) on a side, and it is repeated every 200 mil (5.08 mm) over a wafer. The pattern contains diodes, transistors, MOS capacit sheet resistors, contact resistors, etch-control structures, and a surface profilometer structure. The large blank area is intended for Hall effect measurements once the wafer is scribed and broken into chips. The structures discussed in the following sections are the large base-collector gated diode (3.10),* the small base-collector gated diode (3.14), the collector MOS capacitor (3.8), the collector four-probe resistor (3.17), and a variety of sheet resistors (3.11, 3.22, 3.28, and 3.30). Four sheet resistors in each of the patterns across a wafer were measured and the results displayed in figure 2. Sheet resistance values obtained from the van der Pauw [4] structures (3.11, 3.22, and 3.30) are comparable, which is expected since sheet resistances determined from symmetrical van der Pauw struc- ! tures are independent of geometry. Values obtained from the bridge structure are low because, in the computation of the sheet resistance, the width was assumed to be the same as the photomask dimension, W(mask) = 1.50 mil (38.1 μm) This point was explored further by combining sheet resistance measurements from the bridge (3.28) and van der Pauw (3.22) structures which are depicted in figure 3. The effective width of the bridge structure is given by = We where aX; accounts for lateral diffusion and Woe accounts for lateral over-etch The van der Pauw measurement yields the sheet resistance directly. This was combined with the nearest-neighbor bridge measurement to obtain We. The basediffusion-window width, W, was calculated from W axj. Values for W are shown in figure 4 as a function of position across a wafer for three different etch times. For these measurements aXj. = 0.02 mil (0.5 μm) where a = 0.3 [5]. The width of the bridge structure was also determined from photomicrographs, and the results, shown as solid data points, are in good agreement with the values derived from electrical measurements. The effective width, We, of the bridge structure for the 3 min etch equals the window width, W = 1.57 mil (39.9 um), plus aX; or 1.59 mil (40.4 um). This value is 6 percent larger than the photomask dimension, W mask). The difference between We and W (mask) is important in the design of diffused integrated circuit resistors. Also apparent in figure 4 is the fact that electrical measurements can resolve dimensions smaller than 10 μin (0.25 μm). In addition these electrical dimensional measurements are inexpensive, especially when acquired by automatic probing machines. These measurements are discussed more fully elsewhere [6]. The orthogonal van der Pauw structure (3.22) shown in figure 3 is depicted in greater detail in figure 5. A mathematical model was developed for this structure to determine if a geometrical correction factor is needed in calculating the sheet resistance from the van der Pauw formula. The Laplace equation was solved with the use of finite-difference methods for the geometry shown in the lower part of figure 5 where the bonding pad areas were replaced by shorts on the ends of the arms. For this structure the measured sheet resistance differs from the van der Pauw value by less than 0.1 percent as indicated in figure 6. Here Rs (TRUE) is the true sheet resistance and Rg (VDP) is the sheet resistance determined from measurements with the use of the van der Pauw formula, which appears at the top of figure 6. The curves shown in figure 6 reveal that the side arms may be surprisingly short and wide compared to the active region without requiring as much as one percent correction to the van der Pauw formula. The active region is considered to be a square whose side is S. This study also allows the design of new structures whose active The number following the decimal point refers to a structure shown in figure 3; the number 3 is the test pattern designation. regions are typical of device geometries. For example, the cross structure (D/S = A/S = 1) has a small error and can be fabricated with the use of minimum line width. 3. BULK DOPANT DENSITY Dopant densities were determined in the collector (or bulk) region of a basecollector diode with the use of the junction C-V method [7]. As shown in figure 7, the diode (3.10) is gated and contains an inversion stop (labeled emitter). The dopant profiles for the gated diode are shown in figure 8 where incorrect profiles appear if the gate bias is improper. The proper gate bias is -5.5 V which corresponds to the flat-hand condition for an equivalent MOS capacitor structure. This allows the peripheral junction capacitance to be approximated by a quarter toroid. The diode used in this study was 17 mil (430 μm) in diameter. Profiles can also be obtained with the use of a smaller diode (3.14) such as shown in figure 9 where again the base contact is confined within the base diffusion. This allows the measurement of correct capacitance values. An intercomparison of profiles for large and small diodes is shown in figure 10 where the peripheral correction brings the profiles of both diodes into agreement. Dopant densities were also determined in the collector region of a collector MOS capacitor (3.8) as depicted in figure 11 with the use of the MOS capacitor C-V deep depletion method [8]. A dopant profile shown in figure 12 indicates the presence of phosphorus pile-up at the surface. The dopant density derived with the use of the MOS capacitor Cmax-Cmin method [9] is indicated as 1.04 x 1016 cm-3. This value is considerably different from the bulk value of 6.28 x 1015 cm-3. The resistivity of bulk collector regions was determined [10] with the use of the collector four-probe resistor (3.17) shown in figure 13 where current points are denoted 11 and 12 and voltage points are denoted V1 and V2. The structure is essentially a piped-transistor where the emitter is connected to the collector through a hole in the base. The base, which surrounds the structure, effectively shuts off surface currents forcing currents to flow in the collector region. The probe spacing is 2.25 mil (57 um) which is small compared to the wafer thickness [~ 10 mil (25 μm)] so that back-side shorting effects are negligible. The resistivity versus dopant density relation is depicted in figure 14 for -type silicon in terms of the normalized difference between the Irvin curve and the Caughey-Thomas [11] closed-form formula. It is seen that the CaugheyThomas formula fits the Irvin curve to within +6 percent over the dopant density range from 101 to 1020 cm ̄3. Experimental data, which were determined by the above described methods, were compared to the Caughey-Thomas relation as shown in figure 15. If one ignores the high MOS capacitor values, where experimental difficulties were experienced, the data are within ±6 percent of the Caughey-Thomas relation. tion data. The nature of For p-type silicon the situation is much less satisfactory. the resistivity versus dopant density problem is shown in figure 16 for the case of p-type silicon. The traditionally used curve is that developed by Irvin [1]. More recently Wagner [2] developed another curve to fit ion implantaIn the range of dopant densities between 1017 and 1018 cm-3, these curves differ in resistivity by more than 50 percent. The data points represent experimental results based on junction C-V, Hall effect, and four-probe measurepents taken in conjunction with the American Society for Testing and Materials (ASTM), Committee F-1 on Electronics. These data tend to follow the Wagner curve. The impact of the different curves shown in figure 16 on device design is shown in figure 17 where the surface density for a Gaussian diffusion is calculated from a knowledge of the background density, the sheet resistance, and the junction depth. It is seen that the surface density near 1018 cm3 differs by a factor of two depending on the choice of the resistivity versus dopant den |