characterized and kept under suitable control. Next, the silicon surface after wafer slicing must be maintained free of contamination and particles. In addition, the

surface should have the proper crystal orientation and be relatively free of stress. Finally, subsequent substrate processing steps such as buried collector preparation and epitaxial film deposition must be controlled. In the latter case, all considerations applicable to the original crystal bulk and surface apply, but in addition, analysis and control of the dopant profile become increasingly important.

As indicated above, methods of analysis used to characterize the properties of the silicon substrate are well known. Of course, as larger slices are used and more complex circuit structures are developed, the analytical techniques may have to be refined. Since

this area of integrated circuit fabrication is probably under better control than the others, no specific examples will be presented here. However, the reader is referred to a general reference on the subject of surface characterization [2].

(B) Thermal Oxidation

Thermal silicon dioxide (SiO2) is the basis for today's semiconductor devices and integrated circuits. It provides passivation for active device regions that is not equaled by other types of dielectric layers generally prepared by deposition techniques. The thermal oxidation kinetics and properties have been characterized in a satisfactory manner so that devices with predictable properties may be produced. Included in this characterization are the electrical properties as determined by the four types of oxide charges. These charges are Qss, the fixed oxide charge; Nst, fast interface states; Qo, mobile ionic charge; and Not, radiationinduced charge. While the empirical dependence of these charges on processing variables is well known, a number of questions remain as to their exact origin and physical nature [3]. Indications of how these charges may be investigated using analytical beam techniques are as follows. Figure 3 depicts a cross-section of a thermal silicon oxide as oxidation is proceeding. Also included in the figure is the general relationship for the thermal oxidation process. It can be noted that a thin oxide region at the Si02-Si interface is shown to contain partially ionized silicon. It is believed that the ionized or excess silicon in this region is the origin of Qss, the fixed oxide charge. However, investigators to date

have not verified this origin and additional work needs to be done. An example of the type of analysis that can be employed is shown in Fig. 4. Here, an analysis of the Si/0 ratio in a thermal oxide has been obtained using the ion backscattering technique [4]. Although it is not clear in the figure, the data indicate that a thin layer of about three atomic layers is present which contains a silicon rich oxide. This is compatible with the Qss origin model described above. However, it is clear that additional characterizations and analyses are required to provide a satisfactory understanding of this phenomenon.

The same questions arise regarding origin of Nst, the fast interface states. These states or charges may have a similar origin to Qss' but since they are in electrical communication with the silicon, they can respond to changes in surface potential. While much is known about Qss and Nst, the question of their origin is still quite thought-provoking and presents a challenge to those involved with beam analysis.

Similar questions may be asked about the physical nature of Qo, mobile impurity ions. These ions, which include sodium, lithium, potassium, or hydrogen protons, have long been a source of instabilities in semiconductor device fabrication. A recent development has been the incorporation of a chlorine species in the oxidation process. This chlorine has been reported to "cure all ills" in areas of ionic instability, dielectric breakdown, junction leakage, fast state generation, and others. An example of a verified improvement is shown in Fig. 5, where MOS device drift is almost eliminated in two cases of sodium contamination [5]. Auger analysis is being used to determine some of the compositional properties of these chlorine-containing oxides as shown in Fig. 6, as reported by Cho et al [6]. However, many additional questions remain concerning ion instabilities, in general, and even effects of the analysis technique on the impurity profiles themselves have been noted. Thus, another challenge is presented to materials analysis scientists.

The identification of the origin and elimination of Not, the radiation induced charge is no exception to the discussion presented above. Much time and money have been expended on this subject over the past ten or more years, and many questions still remain. In Fig. 7, Gwyn [ 7 ] summarizes some of the different "cures" for radiation hole trapping in oxides. These proposed solutions include, optimizing oxidation conditions, incorporating species such as aluminum or chromium in the oxide, or even the use of mixed oxides or

dielectrics. The need for developing

analytical beam techniques for identification of radiation charge origin and elimination mechanisms is obvious, if we are to be able to produce MOS devices that will withstand radiation environments.

In addition to oxide charges, other areas of thermal oxidation that need to be controlled or better characterized are oxide integrity, complex oxide-silicon interfaces and dopant impurity redistribution. These will be briefly discussed in later sections.

(C) Photomasking and Cleaning

Of all the areas of integrated circuit fabrication, none has advanced as rapidly as the photomasking operation. This is demonstrated in Fig. 8, where a single MOS transistor of 1964 is pictured as an insert in a photo of a recently developed calculator chip. The latter, which contains about 10,000 individual transistors, is still not as densely packed as more advanced memory chips. The dimensional scales on the two devices in Fig. 8 are roughly equivalent; the larger circuit being about 150 x 180 mils.

The tremendous increase in complexity of today's circuits results in enormous problems related to carrying out the photomasking process as well as to the associated cleaning treatments. The use of analytical beam techniques for identifying and controlling contamination left over from these processes will become increasingly important. Likewise, methods need to be established for better characterization of the photoresist materials. In addition to electrical instability problems, the question of oxide integrity presents itself. In Fig. 9, Kern has provided an example of how two different types of resists may affect defect formation in the underlying oxides [8]. While the incentive for those involved in materials analysis may not be as obvious or the results as satisfying in this area, it is certain that the effects on device yield and reliability are more significant than in almost any other IC processing step.

(D) Diffusion

One of the oldest processes associated with silicon devices is that of dopant diffusion. Typically in the past, the source of dopants that are deposited on the silicon surface prior to diffusion into the silicon has been a gaseous species transported in a diffusion tube from solids (P205, B203), liquids (POC13) or gases (B2H6). More recently,

other types of sources have been employed, such as doped vapor deposited dielectrics, spin-on oxides and ion implantation. In all cases, the main problem has been to determine the diffusion profile before, and more important, after the subsequent high temperature diffusion steps. Also, it has been important to know what percentage of the doping species is electrically active. Thus, many analytical techniques have been used for obtaining these profiles, as well as to determine anomalies and structural damage to the silicon. An example showing the importance of being able to determine dopant profiles is shown in Fig. 10, where the depth of a dopant's penetration during ion implantation is determined by the type of dielectric on the silicon surface [9].

Closely related to the diffusion process and requiring similar types of profile analysis are impurity gettering, and redistribution of dopants during oxidation. In the case of gettering, unwanted metallic impurities, such as copper, iron, nickel, and the like are removed by a complexing action at high temperatures with a species such as phosphosilicate glass. A knowledge of the distribution of these impurities before and after gettering is important. Likewise, the changing dopant profiles in the silicon due to redistribution during thermal oxidation must be known in order to end up with the proper device electrical properties. It has been difficult to accurately predict and verify redistribution profiles after just one oxidation treatment. When it is considered that today's integrated circuit processes employ many such treatments, the correct prediction and/or determination of dopant profiles is almost impossible. In Fig. 11, an example is shown where attempts are being made to calculate and determine profiles after just two oxidation steps [10]. It is obvious that much more work, both theoretical and analytical, needs to be done in this area.

Finally all of the above considerations discussed thus far must be put together and then the problems multiplied by some unknown factor when a three-dimensional aspect is considered. This is exemplified by the drawing in Fig. 12, which depicts a device structure employing an oxide or Isoplanar type of isolation. The interface between this oxide and the device silicon now can result in changes in orientation-dependent, oxide charge densities, as well as dopant impurity concentrations, all of which can severely degrade device properties. Furthermore, the difficulty in predicting these interface properties is exceeded only by the difficulty in analyzing them. So it is

obvious that there will be plenty for the materials analysis scientist to do in cooperation with the device engineer, when this complex type of structure is considered.

(E) Dielectric Deposition

Vapor deposited dielectric films are generally used in conjunction with thermal oxides to provide additional improved device properties. These properties include impurity ion masking, increased voltage breakdown, gettering of impurities, and others. Dielectrics most commonly used for these applications are silicon nitride, silicon oxide, aluminum oxide and phosphosilicate glass. While the use of these deposited dielectrics provides improved characteristics, some adverse effects may result. One such effect is an electrical instability due to charge generation. Four general types of charge formation instabilities have been found to be associated with the combination of deposited dielectric films over thermal silicon oxides. These are indicated in Fig. 13. The degree of all these effects is dependent on the structural composition of the deposited dielectrics. Thus, the analysis and control of the film compositions and structures are very important. An example of this effect is shown in Fig. 14. Here, the electrical conductivity of a silicon nitride film is inversely proportional to the ratio of nitrogen to silicon in the film, the latter being a function of the reactant gas ratios during film formation [11]. The conductivity of the Si3N4, thus determines the degree of instability (c) in Fig. 13. The etch rate of the nitride film also is a function of its composition. Many other examples could be given which show the importance of being able to characterize the compositional and structural properties of deposited dielectric films, which can lead to adverse effects on device properties.

(F) Metallization

The metal interconnection system represents a key aspect of integrated circuit fabrication. This metal has typically been pure aluminum, but lately aluminum alloys have been used, as well as inert metals (Pt, Au), refractory metals (Mo, W) and, in the case of MOS circuits, polycrystalline silicon. In the latter case, the films are doped with phosphorus or boron to achieve the required conductivity. As integrated circuits have become more complex, the analysis and control of the metal interconnection systems have been accordingly more important. This has especially been the case with the addition of alloying constituents to the

aluminum for improved electromigration resistance (Cu) and for reducing silicon substrate alloying effects (Si). An example

of effects on the metal film properties due to the addition of these elements is shown in Fig. 15. Here, it is important to analyze and control the precipitate or cluster formation as well as nodule growth [12]. Another example where structural analysis of interconnections is important is that of polycrystalline silicon deposition, as shown in Fig. 16. In this case, X-ray analysis has been used to determine relative amounts of orientation textures which can affect both electrical properties as well as dopant diffusion kinetics [13]. It is felt that satisfactory techniques exist for charactizing these metal films, but that much more work is needed to monitor changes in film structure and composition during various heat treatments and even device operation. In the latter case, reliability aspects become important as chemical reactions occur between the metal films and the environment in the case of nonhermetic packages (see next section).

(G) Chip Protection

Very soon after integrated circuits were developed in the early 1960's, it was discovered that some sort of layer must be deposited over the metallized chip to protect the metal interconnections from mechanical damage during subsequent assembly procedures. Films used for this purpose were plastics, sedimented glasses, and vapor deposited oxides. Later it was found that this same type of chip-protecting film was required to prevent the metal from reacting with moisture and other gases which penetrated plastic packages. At the same time, it was difficult to obtain a film which exhibited all the necessary properties--physical, chemical and electrical--to provide the necessary protection. This is true to a large extent at the present time. One of the most common causes of reliability problems in plastic packaged integrated circuits is metal corrosion.

Many of the above problems result from improper analysis and control of the chip protection film, which quite often contains phosphorus. This phosphorus prevents cracking of the deposited silicon oxide film, but also can react with water to form phosphoric acid. This acid in turn is a common etchant for aluminum. Paulson and Kirk [14] have presented some curves showing optimum phosphorus concentrations for these films, and one of these is shown in Fig. 17. This example helps to point out the requirements for the determination of composition and structure of chip

protection films. An additional difficulty is that of obtaining a proper depth profile of the constituents.

One last type of characterization that is very important in this area involves failure analysis. When integrated circuits are subjected to life tests or fail in actual use, the understanding of the failure mode is very important and may be accomplished by a carefully executed analysis. Such an analysis includes identification of reaction products, and analytical beam techniques can be used very effectively for this purpose.

CONCLUSIONS

If

In summary, we have reviewed the various processing steps of integrated circuit fabrication. In doing so, we have noted the many areas where analytical beam techniques can be used to provide a better control of these processes and the resulting device properties. Many such analyses are being successfully used today, while in some areas, new or improved methods must be developed. priorities are to be stated, those areas of analysis related to device reliability should be listed first. These include chip protection, metallization and control of device electrical properties. Next in importance would be wafer sort yield. In this case, control and characterization of the photomasking and cleaning processes would undoubtedly be the most important factors, since this process area dominates yields of semiconductor integrated circuits today. Finally, it is important that the scientists who are responsible for developing and carrying out the analyses keep in close communication with the IC processing engineers, so that the problems that need to be solved are solved, and that our always limited resources are used most efficiently.

ACKNOWLEDGMENTS

The author wishes to thank A. J. Learn and R. C. McDonald for helpful discussions concerning various aspects of this paper.