Additional analysis of cross-type sheet resistor test structures was completed. These analyses were carried out with the use of the same numerical analysis used previously in the analysis of orthogonal quadrate crosses and offset quadrate crosses (pinwheels) (NBS Spec. Publ. 400-19, pp. 44-45) [96]. Two limiting cases of the cross structure were studied. The relative geometrical errors for these cases were determined by computing the

true sheet resistance, R ̧, and comparing it

with the sheet resistance calculated from the symmetrical van der Pauw formula [91]: R1 (vdP) =

S

where AV =

(π/1n2) (AV/I),

(18)

V2 for a current I passed into I and out of 12 as shown in figures 46 The error, E, is defined as

and 47.

E

0.01

12

When D/S 0, this case reduces to the symmetrical van der Pauw structure and the error goes to zero. If D/S 0.1, the geometrical error associated with this structure is less

than 1 percent. The integral equations for this limiting case had been formulated by Wick [97] but he did not solve and evaluate the equations.

E = (0.590±0.006) exp[-(6.23±0.02)A/S].

(21)

One approach to assurance of built-in component reliability involves the use of a process validation wafer (PVW). This type of wafer is intended to evaluate process and circuit parameter uniformity, and to measure the occurrence of random faults. The PVW is an entire wafer of test structures and is intended to be fabricated along with product wafers on a periodic basis. This approach is a supplement or alternative to a test pattern substituted for an IC chip on a product wafer. As a process characterization tool the PVW can be used to qualify vendors and can serve as a circuit acceptance criterion. The PVW concept has the potential of greatly reducing the user-imposed requirements that now accompany a high-rel component purchase. Various forms of this approach are currently being used by the British Post Office [98] and by a few U.S. Government agencies in the procurement of reliable, custom components.

As an illustration of a microelectronic test pattern under development for use as a process validation wafer, consider the TTL test pattern shown in figure 48. This pattern consists of various test structures which are intended to be tested electrically with a high-speed dc wafer tester. The test structures are arranged so that all structures can be probed by a 2 by 10 probe array (NBS Spec. Publ. 400-25, pp. 41-43). This modular arrangement allows the structures to be called from a computer library and arranged quickly into a new test pattern to fit available space. In addition, the modular concept allows for standardization of each test structure in its entirety including its probe pads which must be an integral part of the test structure.

The TTL pattern is divided into quadrants, each 1.7 mm (67 mil) by 1.3 mm (51 mil). The lower left quadrant contains strings of contacts and metal runs of varying length over oxide steps. The lower right quadrant contains multi-emitter transistors of varying size. These structures are intended to check for random faults such as contact window problems, incomplete metal coverage, and emittercollector shorts (pipes). The two upper quadrants contain process control structures, circuit elements (both transistors and resistors), and NAND gates. Among the process control structures are several versions of the cross sheet resistor (see sec. 7.2.).

The two-level interaction test structure for p+-polysilicon over epitaxial silicon is shown in figure 49. The structure consists of polysilicon lines of various widths extending from the sapphire up onto a silicon island. The design line widths (in mils; 1 mil 25 μm) are indicated outside the pattern. It can be seen that no polysilicon remains for designed dimensions of 0.1 mil (2.5 μm) or less. This suggests that the polysilicon lines are smaller than their designed dimensions by about 0.05 mil (1.2 μm) on a side. It can also be seen directly that the dimensions on top of the epitaxial silicon and on. top of the sapphire are nearly identical, that a severe distortion in the polysilicon occurs at the edge of the epitaxial silicon, and that a discontinuity in the polysilicon at the edge of the epitaxial silicon exists for lines with designed width of less than about 0.3 mil (7.6 μm).

Figure 49. Two-level interaction test struc

ture.

The two-level alignment test structure is shown in figure 50. This structure consists of a trapezoidal polysilicon region over a rectangular silicon island. It is clear that no difficulty exists in determining the intersection point where the trapezoid crosses the rectangle. The index markers are placed on 1.0-mil (25-um) centers. The difference in intersection points on the two sides of the trapezoid in figure 50a is approximately 0.4 mil (10 um) which corresponds to an actual misalignment of about 0.02 mil (0.5 μm). An orthogonal pair of structures can be used for complete alignment measurement as shown in figure 50b. Even when the edge crossing is not ideal, as shown in figure 50c, the crossing points can be determined quite precisely. The resolution of the structure appears from these results to be about 1 uin. (25 nm) when using an ordinary microscope. This structure can also be used as a very ac

eral size of an object (such as a wafer) after some processing step or with temperature. In this case, the upper level would not necessarily be printed but could be simply observed.

An example of some preliminary results from the type II tests is shown in figure 51. This plot shows the distribution of drain current for a p-channel transistor in saturation across approximately 1.5 in. (38 mm) of a 2-in. (51-mm) diameter wafer. Several very interesting features of these data are noted:

1. A significant number of the devices have no output on the scale used;