MATERIALS CHARACTERIZATION BY ELECTRICAL METHODS tion time. Thus, for neutral impurity scat- From the work of Luong and Shaw [31], it is these values, the electron mobility at 300 K 2 × 1017 cm-3 one obtains curve 4 in figure 6 for the electron mobility at 300 K. obtain calculated resistivity-temperature curves for various values of dopant density which can be compared with experimentally determined curves. To make this comparison, resistivity measure- sumption of the phosphorus density, No, in- 3.7. Thermally Stimulated Current and Capacitance Measurements Many Application to Power-Grade Silicon This critical properties of high-power silicon thyristors and rectifier diodes are significantly affected by the presence of impurity and defect centers which cannot be counted or identified by ordinarily used electrical measurements such as resistivity and lifetime. Many such centers, such as heavy metal contamination, irradiation-induced defects, and process-induced defects have been identified by means of their thermally stimulated current or capacitance response, and each defect is noted to have a particular signature. Although the measurement of thermally stimulated current and capacitance is reasonably well established [34-38], several aspects need further development before the tech At other temperatures, it is not convenient where n is the electron density. Therefore, if u is obtained as a function of dopant n density and temperature as described above and n is obtained as a function of dopant density and temperature by solving the charge- "Principally funded by the Energy Research balance equation [23, 24], it is possible to 19 and Development Administration, Division of Electric Energy Systems. MATERIALS CHARACTERIZATION BY ELECTRICAL METHODS nique can be widely applied to the characterization of power-grade silicon; a new task area has been initiated to carry out this work. To date, all measurements reported in the literature have been made in cryostats on small, individual devices scribed from processed wafers bonded onto headers. One objective of the task is the development of apparatus suitable for performing thermally stimulated current and capacitance measurements on whole large diameter silicon wafers. Use of such an apparatus would eliminate the need for further processing of test specimens after wafer fabrication and allow relatively fast feedback of information to the process line. Since it is desired to characterize starting material as well as material at various stages in the device fabrication process, it is necessary to develop procedures for fabricating test structures which preserve the characteristics of the starting material. The possibility of examining starting material was made feasible by the observation that MOS capacitors were just as suitable for the measurement as p-n junctions (NBS Spec. Publ. 400-1, pp. 16-19) and that both structures yielded the same information (NBS Spec. Publ. 400-4, pp. 27-33). However, to exploit this possibility, low-temperature processes for forming the capacitor oxide and gate electrode must be refined; this is a second objective of the task. Application of the measurement technique at various stages in thyristor fabrication is complicated by the fact that not all regions of the device are accessible externally; a third objective of the task is to determine the feasibility of using monitor wafers and special process steps to enable the measurement after all key thyristor fabrication steps. Initial work has concentrated on the first two objectives: A. Whole-Wafer Apparatus. One major component of the whole-wafer apparatus is a large-area, thermally-controlled chuck, optimized for its thermal response and capable of operation over a temperature range from about 80 to over 600 K. The chuck consists of several components as shown in the exploded view in figure 9a. The copper top plate (2) has vacuum grooves for specimen holddown and a hole for attachment of a ther mocouple. A thin insulator plate (3) sepa rates the top plate from the heating-cooling module (4,5). The copper upper section (4) of this module consists of an integral cooling cavity and heater elements. An inverted view of this module with the four 150-W heater elements exposed is shown in figure 9b. The stainless steel lower section (5) encloses the cooling cavity and forms the manifold for the liquid nitrogen coolant; this section is heli-arc welded to the copper section. The lower section has been designed with a thin rib on the circumference to minimize heat transfer to the supporting hardware. The top surface of the heating module (4) is identical (including vacuum grooves and thermocouple hole) to the top plate; for measurements which do not require electrical isolation, the top plate and insulator can be removed to permit faster thermal response. The wafer index-stop (6) may be attached either to the top plate or the heating module. Parallel to the development of the chuck is the modification of an automatic wafer prober to accommodate the chuck and to allow the capability to screen individual devices on a wafer for mobile ion contamination and for oxide integrity before making the thermally stimulated current or capacitance measurements. The prober and associated parts are illustrated in figure 9c together with the mounted chuck assembly (1); the bridge structure (13) to which the probe ring support (14) is mounted has been moved back to separate the probe ring (9) from the chuck assembly (1) for greater clarity of presentation in the photograph. The probe ring, which normally accommodates up to 60 probe manipulators (10) has been modified to allow mounting of an optional multiprobe assembly (11), which can be used in place of separate manipulators to apply bias and temperature stresses to 36 devices on a wafer simultaneously as a convenient method for detection of mobile ion contamination. The separate manipulators are commercial units modified to allow the use of miniature 50-2 shielded coaxial cables which is necessary to minimize the stray capacitance in the input leads to the 1-MHz capacitance bridge. The bellows (12) are used to transport liquid nitrogen to and from the cooling module. In operation, the wafer is placed on the transfer slide (17) and pushed into the enclosure; by means of the vacuum pick-up probe (16), the wafer is transferred from the slide to the top plate of the chuck (2) and aligned to the raised stop (6). Fine adjustment of the wafer alignment with the prober axes can be made by rotating the chuck about a vertical axis through its center by means of the alignment manipulator (15). Figure 10. Thermally stimulated current response of gold-doped silicon MOS capacitors in wafer form. The prober assembly is surrounded by a hermetic enclosure, shown in the exterior view in figure 9d. All components are sealed to the wall of the enclosure with rubber O-rings or gaskets. The top (19) and front (18) viewports have light-tight covers (not shown) to provide a dark measurement environment. The enclosure is constantly flushed and slightly pressurized (6 psig or 40 kPa) with dry nitrogen to minimize room air penetration; the exhaust gases can be monitored for moisture. A microscope (22) is provided to check wafer alignment through the top viewport (19); the microscope support assembly was modified to allow clearance for the viewport between the microscope objective and the wafer (8). The relative spacings and orientation of the probes must be preset, but the vertical adjustment is accessible by means of the probe ring manipulator (20). All the utility ports are located in the back of the enclosure; these include vacuum, heater power, liquid nitrogen, thermocouple signals, prober control interfacing, and dry nitrogen pressurization. Prior to completion of this apparatus, an earlier version (NBS Spec. Publ. 400-4, pp. 39-40) was modified to increase its maximum heating rate to 2 K/s in order to conduct preliminary feasibility studies of measuring thermally stimulated current and capacitance at the wafer level as described below. (R. Y. Koyama and L. M. Smith) MOS capacitors were made with aluminum gates and thermal oxides on n- and p-type silicon doped with gold. The thermal responses of the gold acceptor in n-type silicon and the gold donor in p-type silicon were measured on the unscribed wafers and, as illustrated in figure 10, were found to be the same as those reported in the literature for measure MATERIALS CHARACTERIZATION BY ELECTRICAL METHODS phase II response, at higher temperatures, is very different from the normal response. Following a bias-temperature stress on the capacitor which drove any mobile ions which were present in the oxide to the metal-oxide interface, the normal response of the gold acceptor was obtained. This response, shown as curve b in the figure, has the phase I shoulder at about 225 K and the phase II peak at about 280 K. If the mobile ions are driven to the silicon-oxide interface by a second (reversed) bias-temperature stress, the response again becomes abnormal as shown in curve c of the figure. These results suggest that the presence of mobile charge at or near the silicon-oxide interface greatly affects the charge state or the emission process of the traps in the depletion region of the semiconductor. However, by removing such mobile charge from the interface, it is still possible to obtain the proper thermally stimulated current response. The presence of mobile ion contamination can be determined by means of bias-temperature stress measurements (NBS Spec. Publ. 400-19, pp. 29-30) prior to the thermally stimulated current measurement. (R. Y. Koyama) dopant density, No, in the depletion region; and the flat-band capacitance, Cfb. The flatband voltage, Vfb, was determined directly from Cfb Figure 12 displays typical measured C-V characteristics for each of the oxide types fabricated. For comparison purposes, the C-V characteristics of a standard, dry thermal oxide are also shown in the figure. Theoretical curves [39] are shown as dots for comparison; these points have been shifted along the voltage axis to allow coincidence of V, with fb the experimental value. The silicon-dioxide capacitors (curves a, b, and d) show similar characteristics; the flat-band voltage is negative (indicating a positive surface-state charge) and the experimental curve lies above the theoretical one in the inversion region (indicating interface-state dispersion). By contrast, the tantalum pentoxide capacitor (curve c) shows a negative surface-state charge and the theoretical curve shows higher dispersion than the experiment. Since the dielectric film in this case was very thin, it is not clear that the C-V measurement is valid because of the possibility of leakage in the oxide; hence, it is possible that the devices goes into deep depletion rather than to true inversion. (F. H. Brewer, R. Y. Koyama, J. Krawczyk, Y. M. Liu, and D. A. Maxwell) At this time, due to the ease of in-house fabrication, the CVD silicon dioxide is the most promising low-temperature oxide. However, neither the anodic silicon dioxide or the tantalum pentoxide processes have been eliminated from consideration. The low-temperature processing procedure was further tested with a lot of n-type, 10 .cm <100> silicon wafers which had been diffused with gold to introduce the known gold acceptor [38]. These simulated starting wafers were then processed with a 400°C CVD oxide and 500°C microalloyed aluminum metallization. Thermally stimulated current measurements were made on these capacitors in the modified wafer apparatus. Although detailed measurements were not made, the response of the gold acceptor was clearly observed. These results indicate that the MOS structure used in these measurements is a suitable vehicle for detecting defects in the starting material. (R. Y. Koyama) The microalloy step is necessary with aluminization using an e-gun source. This is done |