measurements, and to present selected test structure results from a wafer fabricated with an n-p-n transistor process. The resistivity-dopant density relation for silicon is commonly taken from the experimental data of Irvin [2]. Caughey and Thomas [3] have written closed-form mathematical formulas which fit the Irvin data for both n- and p-type silicon. Recently, Wagner [4] has indicated that the p-type relation is in error by about 50 percent for dopant density near 1018 cm-3. NBS has undertaken to reevaluate the resistivity-dopant density relation at the request of and in conjunction with ASTM Committee F-1 on Electronics. The main test vehicles are silicon wafers on which test pattern NBS-3 is fabricated. Preliminary results of our investigation are presented elsewhere [5]. The test structures found on test pattern NBS-3 are listed in table 1. The overall pattern, shown in figure 1, is fabricated on a square silicon chip 200 mil (5.08 mm) on a side where four mask levels were used. Enlarged views of the test pattern are shown in the Appendix. Four different masks were designed and are intended to be used in the following sequence: BASE, EMITTER CONTACT, and METAL. Provision was made in the design to allow for the incorporation of a fifth PASSIVATION mask. The BASE mask delineates regions whose conductivity type is opposite from the collector substrate, and the EMITTER mask delineates regions whose conductivity type is the same as the collector substrate. A BASE (modified) mask was designed to address a special problem with structures 3.12, 3.17, and 3.18. These structures have small collector contacts which are formed by blocking the large-area base diffusion at the contact points. This allows the formation of a collector pipe which reaches through to the top silicon surface. In order to block the base diffusion at a contact point, a base-oxide island is formed which is a square 0.25 mil (6.4 μm) on a side. by 0.10 mil (2.5 μm) (3.8 μm) on a side. This means that the base lateral diffusion must be less than 1.9 μm to prevent the closing off of the collector pipe. To reduce this problem, a BASE (modified) mask was designed where the 41 square base-oxide islands, found on structures 3.12, 3.17, and 3.18, were increased to 0.50 mil (12.7 μm) on a side. When the BASE (modified) mask is used, the lateral diffusion can be as large as 5.1 μm assuming that the base-oxide is overetched by 0.10 mil (2.5 μm). During fabrication, the base-oxide island is over-etched which reduces the oxide island to a square 0.15 mil The chip is composed of an array of 33 test structures such as sheet resistor MOS capacitors, p-n junctions, bipolar and MOS transistors, and etch control resolution structures which for the most part are adaptations of commonly use configurations. It should be noted that the collector Hall effect resistor (3.26) is functional only after it has been scribed from the wafer and the backside metal removed. To accommodate this structure, the scribe grid was omitted from the BASE and EMITTER masks and included on only the CONTACT mask Structures specifically designed for the resistivity-dopant density evaluatic are indicated by asterisks in table 1. Bulk collector dopant density values can be determined from the following structures: MOS capacitor over collectc (3.8), base-collector diode (3.10), and collector Hall effect resistor (3.26) In obtaining dopant density values from the MOS capacitor over collector, the high frequency C-V deep depletion method [6] provides true bulk values. high frequency C-V Cmax-Cmin method [7] can give erroneous values since this method is influenced by the redistribution of impurities at the oxide-silicor interface during the oxidation process [7]. Values obtained from the collector Hall effect resistor (3.26) rely on a knowledge of the scattering factor [8], [9] which is not well established in p-type silicon [8]. Dopant density values can be obtained from the base-collector diode (3.10) by using the junc tion C-V method [10]. Bulk resistivity values can be found from the collector resistors (3.1, 3.7, 3.12, 3.17, and 3.18) and the collector Hall effect resistor (3.26). Collect * resistors (3.1, 3.7, 3.12, and 3.18) are intended to operate with current passing from the top of the chip to the backside contact. In this mode, backside contact resistance and geometrical factors must be determined. € Collector resistors 3.12 and 3.18 yield information about the backside contact resistance, and collector resistor (3.7) was designed to have a readily calculable geometrical factor. The collector four-probe resistor (3.17) is : a conceptually simple structure, but it requires the fabrication of a bipolar I transistor. This device is easy to measure and provides unambiguous bulk - resistivity values which do not depend on a knowledge of the backside contact ! resistance. The collector Hall effect resistor (3.26) can yield unambiguous resistivity values but, as noted above, it requires that wafers be scribed into chips and the removal of the backside metallization. Resistivity and dopant density values can be obtained continuously from base profiles by combining the results of two test structures. The base dopant density profiles can be obtained from the emitter-base diode (3.9) with use of the junction C-V, method and the base resistivity profile can be obtained from the tetrode transistor (3.6). With the use of methods described elsewhere [11], these two structures allow resistivity values to be determined over several decades in dopant density. Many of the remaining test structures are in support of the above structures. They are intended to assure that proper fabrication steps were followed and to aid in diagnosing problems. 2. DESIGN In designing the test structures for test pattern NBS-3 the following design rules were observed: 1. 2. Minimum stripe width: 0.25 mil (6.4 μm). Minimum base to channel stop separation: 0.50 mil (12.7 μm). 3. Minimum emitter to base separation: 0.50 mil (12.7 μm). 4. 5. 6. 7. 8. 9. 10. 11. Minimum contact to base (or emitter) separation: 0.50 mil (12.7 μm). Metal overlap at contacts: 0.25 mil (6.4 μm) [0.50 mil (12.7 μm) where a passivation layer is opened]. Minimum field plate overlap at diffusions: 0.50 mil (12.7 μm). Minimum metal separation: 0.50 mil (12.7 μm). Exposed bonding pad width when a passivation layer is used: 4.00 mil Minimum passivation overlap at metal: 0.25 mil (6.4 μm). Expanded metallization contacts: avoided where possible by extending diffusions under contacts. Top side contacts: provided whenever possible. 13. The lines on each mask level: uniquely located so that they do not 12. coincide with the lines on another mask level. These rules were chosen to minimize problems encountered in pinhole shorting, mask aligning, probing, bonding, and inspecting. For instance, a misalignment of 0.25 mil (6.4 μm) between the CONTACT and METAL masks and between the CONTACT and BASE masks is tolerable. Eliminating expanded metal contacts reduces pinhole shorting problems associated with contacts. Unique location of lines on each mask level simplifies inspection procedures. These design rules eliminate certain fabrication faults and thereby improve the chances that a test structure will function properly. Test *Collector resistor (FP, CS) MOS capacitor over base NBS logo *Tetrode transistor *Collector resistor (DGR) *MOS capacitor over collector (FP, CS) *Emitter-base diode (FP) *Base-collector diode (FP, CS) Base sheet resistor (VDP, FP, CS) Base-collector diode (FP, CS) MOS transistor *Collector four-probe resistor MOS capacitor over collector Emitter sheet resistor (B) Base sheet resistor (B) Surface profile structure Incremental base sheet resistor (VDP) Resolution structuresb 14 4.10 3.33 Metal step-coverage resistor = bridge; CS channel stop; DGR = diffused guard; FP = field plate; N = negative photoresist; P = positive photoresist; VDP van der Pauw. = B = BASE mask; E = EMITTER mask; C = CONTACT mask; M = METAL mask. Structures designed for the resistivity-dopant density evaluation. Figure 1. Test pattern NBS-3 fabricated with the BASE (B), EMITTER (E), CONTACT (C), and METAL (M) masks. The length of the pattern along one side is 200 mil (5.08 mm). 3. TEST STRUCTURES In sections 4 through 8 each test structure is described along with the intended purpose. The structures are grouped in five major categories: resistors, MOS capacitors, diodes, transistors, and miscellaneous. Formulas for calculating such quantities as resistivity, dopant density, and sheet resistance are presented where applicable. The symbols used in the following text are explained at the bottom of table 1 or are indicated on the relevant test structure. In the following sections both a detailed top view layout and cross sectional view of each test structure are given. Figure 2 illustrates the scheme used. In the top views the distance between grid lines represents 0.50 mil (12.7 In the cross sectional views, metal regions are black and oxide regions are dotted. Emitter regions are clear and indicated by a solid line one unit below the silicon surface. Base regions are clear and indicated by a solid line two units below the silicon surface. (In these views a unit is the distance between adjacent grid lines. Also the silicon surface is assumed to be flat for the sake of simplicity; the incorporation of silicon into the oxide during thermal oxidation has been ignored.) Figure 2. An illustration of the notation used in the In the text the term emitter applies to both bipolar transistor emitter regions and to channel stop (CS) regions. The term base applies to both bipolar transistor base regions and to MOS transistor source-drain regions. Emitter and collector refer to regions with the same conductivity type which is opposite from the conductivity of base regions. The emitter is more heavily doped than the collector. |