4.3.

4.4.

Base Sheet Resistor (VDP, FP, CS), Structure 3.11

Incremental Base Sheet Resistor (VDP), Structure 3.30

9

10

4.5.

Emitter Sheet Resistor (VDP), Structure 3.21

11

4.6.

4.7.

4.8.

4.9.

4.10.

4.11.

Emitter Sheet Resistor (B), Structure 3.27

Metal Sheet Resistor (VDP), Structure 3.20

Metal-to-Base Contact Resistor, Structure 3.24

Metal-to-Emitter Contact Resistor, Structure 3.23

Metal Step-Coverage Resistor, Structure 3.33

Collector Resistor (FP, CS), Structure 3.1

4.12. Collector Spreading Resistor (Small), Structure 3.12

4.13. Collector Spreading Resistor (Large), Structure 3.18

14

15

16

17

4.15. Collector Four-Probe Resistor, Structure 3.17

MOS Capacitor Over Collector (FP, CS), Structure 3.8

21

Figure 1.

Test pattern NBS-3 fabricated with the BASE (B), EMITTER

(E), CONTACT (C), and METAL (M) masks. The length of the

pattern along one side is 200 mil (5.08 mm) .

5

Figure 2.

An illustration of the notation used in the cross sec-

tional view of a test structure. The distance between

grid lines is 0.50 mil (12.7 μm). In the top view B =

base, E = emitter, and C = collector

6

Figure 3.

Cross sectional view of a diffused region showing various

dimensions

8

Figure 4.

Photomicrograph of the metal-to-base contact resistor,

structure 3.24

13

Figure 5.

Etch-control structure where the regions within the squares

were etched out so as to increase the size of the squares

to the dotted lines ..

33

Figure 6.

The surface contour of the surface profilometer structure

3.29. The vertical scale factor is 50.0 nm/division and

the horizontal scale factor is approximately 10 μm/divi-

sion. The A through G substructures are described in

section 8.1 . .

38

PREFACE

The work was conducted as part of the Semiconductor Technology Program at the National Bureau of Standards. Portions of this work were supported by the Defense Nuclear Agency (IACRO 75-816), Defense Advanced Research Projects Agency (Order No. 2397), U.S. Navy Strategic Systems Project Office (IPR SP-75-4), and the NBS.

In the semiconductor industry it is common practice to design photomasks in English units. The photomasks used in this study were laid out in English units. The equivalent metric unit is given in parentheses; in some cases the equivalent is rounded off to an appropriate number of significant figures.

MICROELECTRONIC TEST PATTERN NBS-3 FOR EVALUATING THE RESISTIVITY-DOPANT DENSITY RELATIONSHIP OF SILICON

by

Martin G. Buehler

Abstract: Test pattern NBS-3 is a microelectronic
test vehicle designed by the National Bureau of Standards
to evaluate the electronic materials used in discrete
semiconductor devices and integrated circuits. Designed
for fabrication on silicon wafers, the test pattern is
an aid in better understanding integrated circuit fabri-
cation technologies. The main pattern consists of four
masks designated BASE, EMITTER, CONTACT, and METAL and
contains 33 test structures such as sheet resistors, MOS
capacitors, p-n junctions, bipolar and MOS transistors,
and etch control and resolution structures.

The pattern was designed primarily to aid in the evaluation
of the relationship between resistivity and dopant density
in both n- and p-type silicon. This relation is needed
in the design of silicon solid-state devices and in the
analysis of various physical measurements. Other test
structures are included for use as diagnostic tools to
verify that proper fabrication procedures were followed.
The remaining structures allow the exploration of new de-
signs and measurement methods.

The structures are arranged in a square pattern 200 mil
(5.08 mm) on a side. A detailed layout of each test
structure is presented including both a top view and a
cross sectional view. A description of each structure
is given and where applicable the formulas for evaluating
such quantities as resistivity, dopant density, and sheet
resistance are given. The fabrication of the test pattern
is illustrated by an n-p-n transistor process and values
obtained from various test structures are presented.

Key Words: Dopant density; microelectronics; MOS
capacitors; n-p-n transistor fabrication; p-n junctions;
resistivity; semiconductor electronics; sheet resistors;
silicon; test pattern; test structures.

This test pattern follows in a series of microelectronic test patterns intended for use in the design, process control, and product assurance of discrete devices and integrated circuits. The use of these patterns by manufacturers is expected to lead to lower cost and more reliable electronic components. When fully developed, they are intended to be utilized by the buyers of microelectronic components in purchase specifications. The previous pattern, NBS-2 [1], was designed so that we could fabricate various test structures needed for the development of various measurement methods. Test pattern NBS-3 was designed primarily to evaluate the resistivity versus dopant density relation in n- and p-type silicon. Other secondary purposes include the evaluation of test structures for use as process control tools and the development of new and improved test structures. The purpose of this report is to describe the test structures found on test pattern NBS-3, to indicate the test methods associated with the dopant density and resistivity