Semiconductor Measurement Technology:
Planar Test Structures for
Characterizing Impurities in Silicon

U.S. DEPARTMENT OF COMMERCE, Rogers C. B. Morton, Secretary
James A. Baker, III, Under Secretary

Dr. Betsy Ancker-Johnson, Assistant Secretary for Science and Technology
NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Acting Director

Library of Congress Cataloging in Publication Data

Main entry under title:

Planar test structures for characterizing impurities in silicon.

(Semiconductor measurement technology) (National Bureau of
Standards special publication: 400-21)

"Presented as an invited paper at the Large-Scale Inter-
gration (LSI) Process Technology/Semiconductor Preparation
and Characterization Session of the Electrochemical Society Meet-
ing in Toronto, Canada on May 14, 1975."
Bibliography: p.

Supt. of Docs. No.: C 13.10:400-21

1. Semiconductors-Testing-Congresses. 2. Silicon-Defects
-Congresses. I. Buehler, Martin G. II. Series. III. Series: United
States. National Bureau of Standards. Special publication: 400-21.
QC100.U57 No. 400-21 [TK7871.85] 602'.ls [620.1'93] 75-619390

National Bureau of Standards Special Publication 400-21
Nat. Bur. Stand. (U.S.), Spec. Publ. 400-21, 32 pages (Jan. 1976)
CODEN: XNBSAV

U.S. GOVERNMENT PRINTING OFFICE
WASHINGTON: 1976

For sale by the Superintendent of Documents, U.S. Government Printing Office, Washington, D.C. 20402
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Figure 1.

Figure 2.

Figure 3.

Figure 4.

Figure 5.

Figure 6.

Test pattern NBS-3 [3] fabricated with base (B), emitter

(E), contact (C), and metal (M) masks. The length of

the pattern along one side is 200 mil (5.08 mm)

Base sheet resistance values across a silicon wafer for

both the bridge and van der Pauw structures. The dimen-

sion refers to the active portion of the structures; di-

ameters are indicated for 3.11 and 3.30, the length of

the side of a square is indicated for 3.22, and the width

of the bridge structure is given for 3.28 .

Base bridge and van der Pauw sheet resistor structures.

The center-to-center metal pad spacings are indicated.

The voltage points are denoted V1 and V2, and the cur-

rent points are denoted 11 and 12. The van der Pauw

structure was laid out with orthogonal boundaries to aid

automatic pattern generation

:

Base-diffusion-window width across three silicon wafers

etched for three, six, and nine minutes and measured

by electrical and photographic methods

=

The orthogonal van der Pauw sheet resistor structure

and its mathematical equivalent geometry. The dimen-

sion S = 1.5 mil (38 μm), A/S 1/3, and D/S = 1/6.

Influence of geometrical factors on the orthogonal van

der Pauw sheet resistance measurement as determined by a

theoretical calculation. In the van der Pauw formula,

Rs (VDP), AV is V1-V2 for a current I passed into I1 and

out of 12 as shown in the van der Pauw structure of fig-

ure 3 .

Figure 7.

Cross sectional view of the large base-collector diode

(3.10)

Figure 8.

Figure 9.

Junction C-V apparent dopant profiles taken with the use

of the gated diode (3.10) shown in figure 7 biased with

various gate voltages, VG

Cross sectional view of the small base-collector gated

diode (3.14) .

5

6

7

8

9

10

11

12

13

14

Figure 10.

Figure 11.

Figure 12.

Figure 13.

Figure 14.

Junction C-V dopant profiles taken with the large and
small base-collector gated diodes shown in figures 7 and
9. The corrected profiles illustrate the importance of
the peripheral capacitance correction (wafer B12Ph-1)
Cross sectional view of the collector MOS capacitor
(3.8) ..

MOS capacitor C-V dopant profile taken with the use of
the collector MOS capacitor (3.8) shown in figure 11
(wafer 702). The depletion depth in the silicon for the
inversion condition is Xp, and the Debye length is λņ
Top view and cross sectional views of the collector
four-probe resistor (3.17). The center-to-center metal
pad spacing is indicated on the upper photomicrograph
Normalized resistivity difference versus dopant density
for n-type silicon (300 K) which compares the work of
Irvin [1] and Caughey-Thomas [11] .

Figure 15. Normalized resistivity difference versus dopant density for n-type silicon (300 K) which compares experimental data determined by NBS to the Caughey-Thomas [11] formula.

Figure 16.

Figure 17.

Figure 18.

Resistivity versus dopant density relation for p-type
silicon (300 K). The curves are taken from the work of
Irvin [1] and Wagner [2]. The data points are explained
in the text

Surface dopant density of a p-type Gaussian diffused
layer in uniformly doped n-type silicon as a function
of the product of the sheet resistance (300 K) and
junction depth for various background dopant densities,
NB

Normalized resistivity difference versus dopant density
for p-type silicon (300 K) which compares experimental
data to the Wagner formula [2]. Also shown is a com-
parison between the Caughey-Thomas [11] and Wagner [2]
formulas

Figure 19.

An outline of the thermally stimulated current measure-
ment obtained with the use of a p-n junction

22

Figure 20.

Thermally stimulated current response of the gold donor
located on the n-side of an ntp silicon junction for
various heating rates [13]

23

Figure 21.

Thermally stimulated current response of the gold
acceptor located on the n-side of a p1n silicon junction
for various heating rates [14] .

24

Figure 22.

Thermally stimulated current response of the gold accep-
tor in an n-type silicon MOS capacitor for various heat-
ing rates [14] . .

24

Figure 23.

Thermally stimulated current response of the gold accep-
tor in n-type silicon for a heating rate of 10 K/s and
for various G-factor values (explained in the text) [14].
The current is divided by a factor which includes the
electronic charge, the area of the junction, the deple-
tion width and the gold density

25