sity relation.

The data of figure 16 are replotted in figure 18 to point up the need for additional work in p-type silicon. Even though the data agree better with the Wagner curve than with the Caughey-Thomas closed-form formula of the Irvin curve, significant discrepancies are observed.

4. DEFECT CENTERS

Defect centers, which cause lifetime and leakage current degradation in devices, were measured by the same kind of structures used to determine dopant density profiles. These structures (3.8 and 3.10) are shown in figures 7 and 11, and the class of measurements used to detect the defects is the thermally stimulated current measurements. This measurement method [12] is outlined in figure 19 where the upper curve indicates that a diode is cooled to near liquid nitrogen (LN2) temperature and then warmed back to room temperature (RT). While the diode is at liquid nitrogen temperature the middle curve indicates that the diode is zero biased which charges defects with majority carriers (electrons for n-type or holes for p-type). Reverse bias is applied before the diode is warmed up. The lower curve indicates that during the warm-up cycle, certain defects emit majority carriers which are detected as a current pulse before the diode goes into steady-state leakage.

The thermally stimulated current response of various defect centers is shown in the following figures. In figure 20 the gold donor current peak [13] occurs near 130 K. The exact peak temperature depends on the heating rate. The gold acceptor current peak [14] occurs near 220 K as shown in figure 21. This response is quite different from the gold donor response. As indicated by the rapid rise in the current at higher temperatures, the gold acceptor center is th source of junction leakage. The response of the gold acceptor shown in figure 21 was observed in a pn junction. A similar response [14] was observed in an n-type MOS capacitor as shown in figure 22. In addition to the peak at 220 K a second peak occurs near 290 K. This higher temperature peak occurs as the MOS capacitor depletion region changes from its deep depletion width to its steady-state inversion width. From a theoretical model of the thermally stimulated current, the shape of the gold acceptor response depends on the fraction, G, of the depletion region over which defects are charged. This is illustrated in figure 23 where for G 1 all defects in the depletion region are initially

=

charged and for G = 0 none of the defects are charged.

5. CONCLUSIONS

As part of a project to provide the semiconductor industry with well-designed and miniaturized structures for use in process control, various test structures and associated measurement methods were studied. Measurements of large and small van der Pauw structures and gated diode structures were shown to yield the same result. The geometrical design criterion for the orthogonal van der Pauw structure was established. Combination of electrical measurements from bridge and van der Pauw structures yields values for the base-diffusion-window width with high spatial resolution.

The resistivity-dopant density relation for silicon is being up-dated for use device design. Initial preliminary results suggest that for n-type the Caughey Thomas formula and for p-type the Wagner formula appear to be the best available in the current literature.

Simple test structures can be used to detect and identify lifetime and leakage centers. The thermally stimulated current response of gold in silicon leads to its rapid identification as a contaminant in p-n junctions and MOS capacitor

The authors are indebted to R. Y. Koyama for establishing the MOS capacitor
C-V deep depletion method and for the data appearing in figure 12, and to
W. M. Bullis for a critical reading of the manuscript.

L.

2.

3.

4.

5.

6.

7.

8.

Irvin, J. C., Resistivity of Bulk Silicon and of Diffused Layers in
Silicon, Bell System Tech. J. 41, 387-410 (1962).

Wagner, S., Diffusion of Boron from Shallow Ion Implants in Silicon,
J. Electrochem. Soc. 119, 1570-1576 (1972).

Buehler, M. G., Semiconductor Measurement Technology: Test Pattern
NBS-3 for Evaluating the Resistivity-Dopant Density Relation in
Silicon, NBS Special Publication 400-22 (in preparation).

van der Pauw, L. J., A Method of Measuring the Resistivity and Hall Coefficient on Lamellae of Arbitrary Shape, Philips Research Reports 13, 1-9 (1958).

Penny, W. M. and Lau, L., eds., MOS Integrated Circuits, pp. 113-116 (van Nostrand Reinhold Company, New York, 1972).

Buehler, M. G. and David, J. M., Bridge and van der Pauw Sheet Resistors for Characterizing the Sheet Resistance and Oxide Window Width of Diffused Silicon Layers (to be submitted for publication).

Buehler, M. G., Peripheral and Diffused Layer Effects on Doping Profiles, IEEE Trans. Electron Devices ED-19, 1171-1178 (1972).

van Gelder, W., and Nicollian, E. H., Silicon Impurity Distribution as Revealed by Pulse MOS C-V Measurements, J. Electrochem. Soc. 118 138-141 (1971).

9. Deal, B. E., Grove, A. S., Snow, E. H., and Sah, C. T., Observations of Impurity Redistribution During Thermal Oxidation of Silicon Using the MOS Structure, J. Electrochem. Soc. 112, 308-314 (1965).

0. Uhlir, A., Jr., The Potentials of Infinite Systems of Sources and Numerical Solutions of Problems in Semiconductor Engineering, Bell System Tech. J. 34, 105-128 (1955).

.1.

2.

Caughey, D. M. and Thomas, R. E., Carrier Mobilities in Silicon Empirically Related to Doping and Field, Proc. IEEE 55, 2192-2193 (1967).

Buehler, M. G., Thermally Stimulated Measurements: The Characterization of Defects in Silicon p-n Junctions, Semiconductor Silicon 1973, H. R. Huff and R. R. Burgess, eds., pp. 549-560 (Electrochem. Soc., Princeton, N.J., 1973). This technique is also described in a videotape: Buehler, M. G., Defects in p-n Junctions and MOS Capacitors Observed Using Thermally Stimulated Current and Capacitance Measurements (June 1974) available for loan from H. A. Schafft, NBS, Washington, D. C. 20234.

3. Buehler, M. G., Impurity Centers in p-n Junctions Determined from Shifts in the Thermally Stimulated Current and Capacitance Response with Heating Rate, Solid-State Electronics 15, 69-79 (1972).

14. Buehler, M. G. and Phillips, W. E., A Study of the Gold Acceptor in a Silicon pn Junction and an n-type MOS Capacitor by Thermally Stimulated Current and Capacitance Measurements (to be submitted for publication).

Figure 1. Test pattern NBS-3 [3] fabricated with base (B), emitter (E),

contact (C), and metal (M) masks.

side is 200 mil (5.08 mm).

Figure 2. Base sheet resistance values across a silicon wafer for both the bridge and van der Pauw structures. The dimension refers to the active portion of the structures; diameters are indicated for 3.11 and 3.30, the length of the side of a square is indicated for 3.22, and the width of the bridge structure is given for 3.28.

Figure 3. Base bridge and van der Pauw sheet resistor structures. The center-to-center metal pad spacings are indicated. The voltage points are denoted V1 and V2, and the current points are denoted 11 and 12. The van der Pauw structure was laid out with orthogonal boundaries to aid automatic pattern generation.