Page images
PDF
EPUB
[graphic][subsumed][subsumed][subsumed][subsumed][subsumed][subsumed]

Semiconductor Measurement Technology:
Planar Test Structures for
Characterizing Impurities in Silicon

[merged small][merged small][merged small][merged small][merged small][merged small][merged small][ocr errors][merged small][merged small][merged small][merged small]

U.S. DEPARTMENT OF COMMERCE, Rogers C. B. Morton, Secretary

James A. Baker, III, Under Secretary

Dr. Betsy Ancker-Johnson, Assistant Secretary for Science and Technology NATIONAL BUREAU OF STANDARDS, Ernest Ambler, Acting Director

[merged small][merged small][ocr errors][merged small][ocr errors][merged small][merged small][merged small][merged small]

Library of Congress Cataloging in Publication Data

Main entry under title:
Planar test structures for characterizing impurities in silicon.

(Semiconductor measurement technology) (National Bureau of
Standards special publication: 100-21)

Presented as an invited paper ... at the Large-Scale Inter.
gration (LSI) Process Technology/Semiconductor Preparation
and Characterization Session of the Electrochemical Society Meel
ing in Toronto, Canada on May 14, 1975."

Bibliography: p.
Supt. of Docs. No.: ( 13.10:400-21

1. Semiconductors—Testing-Congresses. 2. Silicon-Defects
-Congresses. I. Buehler, Martin G. II. Series. III. Series: L'nited
States. National Bureau of Standards. Special publication: 400-21.
QC100.U57 No. 400-21 [TK7871.85) 602'.ls (620.1'93] 75.619390

National Bureau of Standards Special Publication 400-21
Nat. Bur. Stand. (U.S.), Spec. Publ. 400-21, 32 pages (Jan. 1976)

CODEN: XNBSAV

C.S. COVERNMENT PRINTING OFFICE

WASHINGTON: 1976

For sale by the Superintendent of Documents, U.S. Government Printing Office, Washington, D.C. 20402 (Order by SD Catalog No. C13.10:400-21). Price 1.30 (Add 25 percent additional for other than U.S. mailing).

[merged small][merged small][merged small][merged small][merged small][merged small][merged small][merged small][ocr errors][merged small][merged small][merged small][merged small][merged small][merged small][merged small][merged small][merged small][ocr errors][merged small]
[ocr errors]
[ocr errors]
[ocr errors]
[ocr errors]
[blocks in formation]

14

Figure 10.

Junction C-V dopant profiles taken with the large and
small base-collector gated diodes shown in figures 7 and
9. The corrected profiles illustrate the importance of
the peripheral capacitance correction (wafer B12Ph-1) ..

14

Figure 11.

Cross sectional view of the collector MOS capacitor
(3.8) ..

15

15

16

.

[ocr errors]

Figure 12. MOS capacitor C-V dopant profile taken with the use of

the collector MOS capacitor (3.8) shown in figure 11
(wafer 702). The depletion depth in the silicon for the

inversion condition is Xp, and the Debye length is in .. Figure 13. Top view and cross sectional views of the collector

four-probe resistor (3.17). The center-to-center metal

pad spacing is indicated on the upper photomicrograph . Figure 14. Normalized resistivity difference versus dopant density

for n-type silicon (300 K) which compares the work of

Irvin (1) and Caughey-Thomas [11]
Figure 15. Normalized resistivity difference versus dopant density

for n-type silicon (300 K) which compares experimental
data determined by NBS to the Caughey-Thomas (11)
formula ..

17

18

Figure 16.

Resistivity versus dopant density relation for p-type
silicon (300 K). The curves are taken from the work of
Irvin (1) and Wagner (2). The data points are explained
in the text .

19

Figure 17.

Surface dopant density of a p-type Gaussian diffused
layer in uniformly doped n-type silicon as a function
of the product of the sheet resistance (300 K) and
junction depth for various background dopant densities,
NB

20

Figure 18.

Normalized resistivity difference versus dopant density
for p-type silicon (300 K) which compares experimental
data to the Wagner formula (2). Also shown is a com-
parison between the Caughey-Thomas [11] and Wagner (2)
formulas

21

Figure 19.

An outline of the thermally stimulated current measure-
ment obtained with the use of a p-n junction

22

[merged small][merged small][ocr errors][merged small]

Thermally stimulated current response of the gold donor
located on the n-side of an n+p silicon junction for
various heating rates [13]
Thermally stimulated current response of the gold
acceptor located on the n-side of a pin silicon junction
for various heating rates (14)
Thermally stimulated current response of the gold accep-
tor in an n-type silicon MOS capacitor for various heat-
ing rates (14) .

24

Figure 22.

24

Figure 23.

Thermally stimulated current response of the gold accep-
tor in n-type silicon for a heating rate of 10 K/s and
for various G-factor values (explained in the text) (14).
The current is divided by a factor which includes the
electronic charge, the area of the junction, the deple-
tion width and the gold density .

25

« PreviousContinue »