because the wafer is centered on the copper block. The vertical motion is accomplished by placing the pivot point of the probe on the same level as the wafer. Another probe system (not shown) is available for system C for making measurements in magnetic fields and is about 0.5 in. (1.3 cm) high so that it can be placed between the poles of a magnet. The data acquisition system (system D) has only recently become operational so its full impact has not been felt. However, it has proved to be especially useful for obtaining the kinds of data that are not easily obtained automatically. The operation flow chart for the computer controlled system (system E) is shown in figure 10. The system is controlled by its own computer (RCA * 70-25). The operator at the tester has available powerful software to interact with the computer. After the data has been reduced, it can be sent to the larger computer (RCA 70-45) to develop correlation, histogram, or 'three-dimensional' plots. A more detailed description of this system is available elsewhere [9]. * With the development of the data acquisition came the development of test patterns for SOS technology. The test patterns used to analyze the processes include MOS capacitors and transistors, metallization cross-over test structures, gatecontrolled van der Pauw structures, and diffused diodes. To obtain information about parameter variations over the wafer, a square test pattern, approximately 13 mils (330 μm) square, is now used. Examples of some of the test structures used are briefly described below. Three test structures have been used to test electrically for mask alignment and thereby obviate the need of a visual inspection for this purpose. The test structure sketched in figure 11 is used to check with a resistance measurement the alignment of a diffusion mask to a silicon island, along one direction. The design of another test structure is shown in figure 12 where the alignment, along one direction, between *Commercial equipment is identified to adequately specify the system used. In no case does identification imply recommendation or endorsement by the National Bureau of Standards nor does it imply that the equipment identified is necessarily the best available for the purpose. silicon. Misalignment of the two pads is electrically detected when the metallization extends beyond the oxide and contacts the diffused silicon. When several such structures with different sized oxide pads are used, a digital measure of alignment can be obtained. A method for electrically measuring process-induced changes in dimensions is useable when films of uniform thickness and resistivity can be fabricated over the extent of the test structure. A sketch of such a structure is shown in figure 14. The starting or designed dimensions, W, and 1d W2d' differ from the actual and final dimensions, W1 and W2 and W2d Wid by a constant amount, 2W introduced by fabrication procedures. Knowing oe' oe at the enlarged artwork stage, W may be obtained by passing a constant current through the structure and measuring the voltage drops, and V along equal 2' lengths, L, on the wide and narrow stripes, respectively. /v. W may be calculated using the following equation, 1' oe Evaluating the ratio a = oe oe 2(1 - a) 2d The value of the current should be sufficiently large to allow accurate measurements of V1 and V2. For adequate sensitivity, the test structure should be designed so that Wld is 3 to 10 times larger than W, and so that W. is 5 to 10 times larger than the 2d' expected value of W and larger than any irregularity of the edges. If the magnitude of the irregularity is of the order of W oe' obtained if L is much greater than W severe, the technique cannot be used. For well-designed structures, a W as small as about 1 μuin (~ 0.03 μm) can be measured. oe accurate measurement of W can still be However, if irregularities in the edge are ое oe Examples of several types of data outputs are described and illustrated next. The first is an example of plotting one parameter against another; in particular, a capacitance-voltage (C-V) plot of an SOS silicon gate MOS capacitor is shown in Woe Wid W2d W 2 Figure 14. Top view of test structure for measuring the difference, 2W figure 15. The plot displays hysteresis, kinks, 'and noise. While it is possible to interpret such data on an individual basis, analysis on a fully automated system would be impractical. Such curves have what is called high structure and are suitable only for plotting on a semiautomatic system. Another type of plot on the semiautomatic system is shown in figure 16 where one parameter is plotted against another with a position variable introduced. Here the drain characteristic at a specific gate voltage along a line on the wafer is illustrated. This plot can be generated directly on an x-y recorder in a matter of 10 minutes without need of a computer. Figure 15. Example of a data output where one parameter is plotted against another. Figure 16. Example of a data output where one parameter is plotted against another with a position variable introduced. An example of a correlation or scatter plot is shown in figure 17 where the field-effect mobility is plotted against carrier concentration, as measured with a capacitor and analyzed automatically. A definite trend is seen but the scatter of data points indicates that other parameters affect the field-effect mobility. A presentation that has been useful is the one shown in figure 18 where the magnitude of a parameter (in this case threshold voltage) over a wafer is indicated by the character used. An asterisk is used for the larger, no character for the lower, and a period for the in-between values of the parameter. The numerical values of the threshold voltage over the wafer may also be printed out. A histogram presentation, aside from missing the trend in the value of threshold voltage over the wafer, might show a standard deviation that would be much greater than would be expected over any one die from the wafer. Another way of displaying data is by way of "three-dimensional" (3D) plots which can reveal correlations more effectively than correlation or scatter plots. The 3D variation of sheet resistance over a wafer is shown in figure 19. In one particular case, a strong correlation between carrier concentration and threshold voltage was apparent with such 3D displays, but the correlation was not as clearly shown in Figure 17. Example of a correlation, or scatter, plot where the field-effect mobility is plotted against carrier concentration. |