power is removed, since the junction temperature is maximum at that time. However, this is not possible because 1) it takes a finite time for the transistor current to decay from the heating value to the measuring value and 2) transients exist in the measuring voltage waveform for some time after the measuring current value is reached due primarily to charge storage effects in the device under test (as discussed in 4.3.3). Because some semiconductor element cooling occurs during this delay period, the TSP may have to be extrapolated back to the time when the heating power was terminated (see Appendix C of Appendix I for details). The extrapolation procedure is based on the assumption that the heat source thickness is small compared to the total chip thickness and that for approximately the first 250 us of cooling one-dimensional heat flow occurs [3]. During this period, a proportionality factor, K, which relates the change in T, during cooling to t1/2 [see eq (1) of Appendix C of Appendix I] can be defined as follows: J t T T J1 I J2 = = = delay time after heating power is terminated, in microseconds, When thermal resistance measurements are being made on a large number of devices of a given design and construction, the use of a simplified extrapolation procedure is often acceptable. Under these conditions and for a given set of device operating conditions (V CE I, and IC' I), the proportionality factor, K, is relatively constant. It was also shown in section 4.4.1 that a single value of the temperature coefficient of the TSP is also appropriate for devices of a given design and construction. Then the extrapolation correction factor (K') is given M The basic relationship used to calculate the thermal resistance [see eq (3)] can be modified as follows to take into account the use of the constant extrapolation correction factor (K'): where V VM2 is measured at time t. (For greatest precision, t should be as small as possible, consistent with t2t t1·) 2 To validate the assumption that a single extrapolation correction factor (K') can be used, the extrapolated slope of the cooling curve should be measured for 10 devices of the same design, construction, and operating conditions as those to be tested. If the relative sample standard deviation of these measurements is less than or equal to ±3 percent, the average extrapolation correction factor can be used in the calculation of thermal resistance for all other devices of that design and construction.* Since the cooling curve during the first 250 μs of cooling is proportional to the area of conduction of the transistor, the use of this simplified extrapolation procedure is not recommended for operating conditions at which current crowding occurs. 5. Thermal Response Measurements for Die Attachment Evaluation' ** Both the steady-state thermal response (or thermal resistance) and the transient thermal response of semiconductor devices are sensitive to the presence of voids in the die attachment material between the semiconductor chip and header since these voids impede the flow of heat from the chip to the case (header). Due to the difference in the thermal time constants of the chip and case, the measurement of transient thermal response can be made more sensitive to the presence of voids than can the measurement of steady-state thermal response. This is because the chip thermal time constant is generally several orders of magnitude shorter than that of the case. Thus, the heating power pulse width can be selected so that only the chip and the chip-to-case interface are heated during the pulse by using a pulse width somewhat greater than the chip thermal time constant, but less than that of the case. Heating power pulse widths ranging from 5 to 10 ms have been found to satisfy this criterion. This enables the detection of voids to be greatly enhanced, with *This validation procedure was developed in conjunction with EIA-JEDEC Committee JC-13.1 on Government Liaison for Discrete Semiconductor Devices for use in a revision of Method 3131 on Thermal Resistance of MIL-STD-750. The revised test method for measuring the thermal resistance of transistors is designated Method 3131.1 and can be found in MIL-STD-750B, Notice 9, dated September 19, 1978. In Method 3131.1, the extrapolation correction factor, K', is labeled K. [See Appendix V of this report for information on the equivalency of symbols used in the commercial and military thermal resistance test methods for transistors.] ** This procedure is incorporated in EIA Recommended Standard RS-313-B, Thermal Resistance of Conduction Cooled Power Transistors, dated October 1975 as Appendix A. (See Appendix I of this report). the added advantage of not having to mount the device under test on a heat sink [5]. To compare relative quality of the die bond, it is assumed that the temperature coefficient of the TSP is the same for all members of a given group of devices of the same design and construction (see section 4.4.1). It is therefore necessary only to measure the TSP first under conditions of no internal power dissipation (V) and then at some specified time MC after the termination of the constant heating power pulse (V). A quanM2 tity proportional to the junction-to-reference point temperature difference is obtained by subtracting VM from V. M2 This allows the transient thermal response technique to be made less time-consuming for use as a manufacturing screen or process control measurement for die attachment evaluation. VMC: A typical circuit for measuring V, and V is shown in figure 6. MC M2 It should be noted that the power interruption circuitry is similar to that used in the measurement of thermal resistance utilizing the emitteronly switching procedure, although for transient thermal response measurements, the power-off interval is long compared to the power-on interval. EE 1 The circuit is controlled by a clock pulse with adjustable width and repetition rate. When the voltage level of the clock pulse is zero, transistor Q1 is off, and the current through the DUT is the sum of the heatQ1 ing current (switch S1 closed) and I. The heating power pulse ends when the clock goes negative. This turns on, causing the heating current from V, to now flow through Q, instead of the DUT. After a delay to allow electrical transients to subside (usually 10 to 50 us), the sampleand-hold unit (S&H) senses V, and displays its value on the digital voltM2 meter (DVM) (switch S, as indicated). The voltage V is obtained by mak3 MC ing the measurement, with the heating current supply disconnected (switch S open) or with transistor Q1 turned on, prior to the application of the heating power pulse. 6. Conclusions A brief description of the idealized concept of thermal resistance has been given along with the problems and pitfalls encountered in applying the concept to power transistors. It was shown that for high-current low-voltage operating conditions, a unique and meaningful thermal resistance based on the peak junction temperature can usually be defined, but for low-current, high-voltage conditions, no unique value, independent of operating conditions, can be defined. In addition, the advantages and disadvantages of various electrical techniques for measuring thermal resistance were described, and a preferred standard technique was discussed in detail. This preferred technique, in which the forward-biased emitter-base junction is used as the temperature-sensitive parameter, is usable on all types of bipolar transistors. The measurement procedure is relatively simple and, because the temperature-sensitive parameter is sensed under conditions that simulate normal device operation, it is relatively accurate. The power interrup EB tion circuitry is also relatively fast and simple since only the emitter terminal of the device under test is switched. Detailed circuit diagrams and mounting and cooling arrangements to enable the building of a completed test system for measuring the thermal resistance of power transistors using the V. emitter-only switching technique are also presented. Simplifications in the temperature-sensitive parameter calibration and extrapolation procedures to make the technique usable in a production environment are valid under a variety of device operating conditions as long as the device design and construction is not changed. The basic approach and test circuitry is also usable for semiconductor device die attachment evaluation. 1. 2. 3. 4. 5. 6. 7. 8. 9. 7. References Thermal Resistance Measurements of Conduction Cooled Power Transistors, EIA Recommended Standard RS-313-B (Revision of RS-313-A), October 1975. (Available from Electronics Industries Association, 2001 Eye Street, N.W., Washington, DC 20006.) (This reference can be found in Appendix I of this report.) Blackburn, D. L., An Electrical Technique for the Measurement of Blackburn, D. L., and Oettinger, F. F., Transient Thermal Response Measurements of Power Transistors, PESC '74 Record, IEEE Power Electronics Specialists Conference, Murray Hill, New Jersey, June 10-12, 1974, pp. 140-148. Rubin, S., Thermal Resistance Measurements on Monolithic and Hybrid Oettinger, F. F., and Gladhill, R. L., Thermal Response Measurements for Semiconductor Device Die Attachment Evaluation, 1973 IEDM Technical Digest, Washington, D. C., December 3-4, 1973, pp. 47-50. Reich, B., Continuous Thermal Resistance Measurements, Semicon- Reich, B., and Hakim, E. B., An Appraisal of Transistor Thermal Resistance, SCP and Solid State Technology 8, No. 4, 21-29 (1965). Early, J. M., Effect of Space Charge Layer Widening in Junction Sparkes, J. J., Voltage Feedback and Thermal Resistance in Junction |