Figure 56. register.

b. Static condition after a single clock pulse was injected through the clock input and a logical one injected via the data input at the lower left of the figure.

a small amount of debiasing of the righthand emitter side is occuring due to the dc voltage drop along the base fingers.

It was also shown that the scanner can be used to observe logic information passing through an MOS shift register without altering the characteristics of the device. Previously, the scanning electron microscope has been used to examine MOS logic circuits [80], but this requires the inconvenience of inserting the circuit into and removing it from a vacuum system. Furthermore, the electron beam can cause catastrophic damage to MOS circuits especially when they are exposed under bias (NBS Spec. Publ. 400-17, pp. 4346) unless special precautions are taken [81]. The shift register was a static dual 128-bit p-MOS ion-implanted device. In order to be able to observe the logic flow in the device with the laser scanner, the package leads were connected as appropriate for normal circuit operation and information which describes the circuit operation was extracted by monitoring variations in power supply current to the device.

Figure 56 shows the pictures of the displays obtained by scanning the p-MOS shift register with the 0.633 um laser at low intensity. Figure 56a shows about one third of one of the 128-bit registers and some associated input/output circuitry. In the main part of the register a random pattern of logical ones and zeros which appear as displaced dark and

light areas can be seen. The logic flows, in this register, along a snake-like path which begins in the left-hand column at the bottom and flows up the column, then down the second column, up the third and down the fourth, where it switches the output circuitry at the bottom of the fourth column.

Figure 56b shows the same register after a single clock pulse has been injected through the clock input and a logical 1 injected via the data input. It can be easily seen upon comparison of the two photographs how the logical ones and zeros have shifted in accordance with the clock pulse. The output has also switched states. Demonstrated here is the operation of a good device, although improper internal operation on a defective device has also been observed. When the circuit was operated with reduced power supply voltage, it was observed that some logic cells did not always function properly.

It was also found while scanning this MOS device that internal logic states can be changed nondestructively by increasing the laser intensity with the polarizer-analyzer combination in the optical system. Logical ones can be selectively changed to zeros and vice versa by decreasing the laser scan raster to a region on the logic cell where a change is desired. The laser is aimed to one side of the logic cell to change a zero to a one, and to the other side to change a one to a zero; aiming the laser is accomplished by

12.

eJC1

termined by measuring the series combination of both emitter-base junction voltages and ReJC1 is the thermal resistance of the input transistor* (NBS Spec. Publs. 400-12, pp. 35-37, and 400-17, pp. 52-55). The experimental results reported previously were made on devices using external emitter-base shunt resistors which had magnitudes which were nearly optimum for directly measuring R and ReJC (1+2) by the emitter-only switching technique [82]. To test this relationship further, measurements were made on a specially fabricated four-terminal Darlington + device with an input diode and integrated emitter-base shunt resistors whose magnitudes and ratio were considerably less than optimum [83].

S

ing method using the emitter-base voltage as the temperature sensitive parameter (TSP) because the ratio of the input shunt resistance to the output shunt resistance was too small (2:1) to allow the input transistor to be turned on while the output transistor was turned off. Therefore, the collector-base voltage of the input transistor was used as the TSP to determine R with the use of JC1 the measuring circuit (NBS Spec. Publ. 40012, pp. 35-37 connected in the grounded-base, emitter-and-collector switching mode with switches S and S4 open, switch S2 closed, and switch S3 set to C as shown in figure 58. During measurement, the series transistor switch Q is turned off and the parallel transistor switch Q is turned on by a clock pulse which also activates a sample-and-hold circuit (not shown) which senses the voltage between terminal C and terminal B1. In this measuring configuration, the measuring current, Im, has two possible parallel paths: via the collector-base junction of the transistor Q1 or via the resistor R1 in series with the collector-base junction of the transistor Q2. The desired path is via Q1, as indicated in the partial circuit diagram in figure 59. However, if R1 is small and Q2 is, as is usual, hotter than Q1, a considerable amount of current may also pass through 92. One way to reduce the effects of the unwanted parallel paths is to make Im larger so that the voltage drop in R1 restricts the percentage of Im that is diverted from Q1. For the device studied, R JC1 sured by this method reached a constant value for I,, ≥ 3 mA.

M

as mea

REE

R2

PARALLEL SWITCH

=

=

tor, ReJC2' by using the collector-base voltage of Q2 as the TSP this measurement was made [83] on the same four-terminal Darlington device with a range of measuring currents in the circuit of figure 58 connected in the quasi-grounded-emitter, emitter-and-collector switching mode with switches S2 and S4 open, switch S1 closed, and switch S3 set to C. The measured value ranged from 2.39°C/W for IM 0.5 mA to 4.16°C/W for Im 24 mA. The reason for this strong current dependence is the multiplicity of current paths available for the measuring current, IM. Among the possibilities are: the series combination of the resistor R2 and the base-collector junction of the transistor Q2 (the desired path shown in figure 60; the series combination of the emitter-base and the basecollector junctions of Q2; the series combination of the resistors R2 and R1 and the base-collector junction of the transistor Q1; the series combination of R2 and the emitterbase and base-collector junctions of Q1. Conduction across the emitter-base junctions is made possible when the junctions are reverse biased by current passing through the appropriate shunt resistor. The relative fractions of current in the various paths depends on the magnitude of Im∙ If a commutating diode were across the output, (as is often the case), the possibilities are even more (S. Rubin)

numerous.

Figure 61.

b.

35-W triple diffused transistor

The percentage of available ac

total active area of the device actually dissipating power at steady-state is noted for each point that was determined by the standard electrical technique.

The steady-state current distribution, and therefore the temperature distribution, is essentially uniform over the entire thermally limited operating range for the 25-W device. This is why the agreement between the three techniques is so good. Note that the electrical peak temperature values agree almost exactly with values determined by infrared microradiometry. The manufacturer has been rather conservative in the thermal rating of this device; the specified SOA thermal limits restrict the power that can be applied to the device to considerably less than that for which the peak junction temperature equals the maximum safe temperature (200°C).

The 35-W device exhibits severe current nonuniformities, and therefore temperature nonuniformities, over a significant portion of the specified SOA. Note that both the infrared microradiometry and electrical peak temperature techniques show that the maximum safe temperature (200°C) can be exceeded within the published SOA limits. This is shown by the points which lie to the left of the specified SOA for Ic ≤ 0.4 A. However, the stan

dard electrical technique would lead one to believe that the specified SOA safely limits the power over the entire range.

For both devices studied, use of the standard electrical technique would appear to permit operation at higher power than either of the other two methods. However, it is well known that the peak junction temperature cannot be measured accurately by standard electrical techniques. Consequently, when this method is used to develop the SOA, the limits are normally shifted toward lower voltages. In spite of this, the resulting limits do not guarantee that the maximum safe temperature will not be exceeded for low current-high voltage operation when current constrictions occur. On the other hand, for high currentlow voltage operation, both devices studied tended to be underutilized in that more power could safely be dissipated than the specified SOA limits permit. The ability to measure the peak junction temperature by a relatively simple electrical method should enable manufacturers to generate more realistic SOA limits and also permit device users to verify more readily the specified SOA limits for particular devices and applications.