5.1. Reevaluation of Irvin's Curves

Resistivity and carrier density measurements were made on additional phosphorus-doped silicon wafers as part of the continuing work on the experimental redetermination of the resistivity-dopant density relation using previously reported procedures (NBS Spec. Publ. 400-17, pp. 13-14). Bulk resistivity was determined from measurements on test structure 3.17, collector four-probe resistor. Electron density was obtained from measurements on test structure 3.8, the MOS capacitor over collector, by the deep depletion method (NBS Spec. Publ. 400-17, pp. 8, 10-11) and from measurements on test structure 3.10, basecollector diode, by the junction capacitancevoltage (C-V) method (NBS Tech. Note 788, PP. 9-11). Electron density data from the junction C-V method were used for calculating the mobility as this method appears to be more reproducible at the present time than the MOS procedure.

The four-probe resistor and the base-collector diode are about 3 mm apart on the test pattern; this can be a source of error in wafers with large resistivity variations. In order to minimize the effects of these variations, mobility is computed from the electron density measured on a diode and the average of the resistivities measured on the two collector resistors on either side of the diode. The procedure is repeated for typically four good diodes in the same general area of the wafer, usually near the center, to arrive at an average mobility as given in table 4. Wafers were screened for radial resistivity gradients by four-probe measurements prior to processing. The maximum varia

APPLICATIONS

0.5

A2.0Ph-2

0.0

83.9Ph-1 B12Ph-1

(1.270±0.048)×1015

-1.3

1306

-0.4

100x(exp)-(calc)]/u(calc)

cases of redistribution than the boundary conditions employed previously (NBS Spec. Publ. 400-1, p. 11, eq (8)).

P

=

Ku [37] has found a closed-form solution to the uniform redistribution problem with the assumption that eq (7), with C 0, holds at the oxygen-oxide interface. His work suggests that the solution to the uniform redistribution problem in the case of zero flux between the oxide and air should possess two qualitative features: (i) that the value of the concentration in the silicon at the moving front be independent of time and (ii) that the concentration in the oxide be spatially uniform and independent of time. The computer program reproduced both these features to several significant figures, except for a very brief period of time near t = 0. The total time taken until these qualitative features set in can be shortened by using smaller time increments, At.

5.3. Dynamic MOS C-V Method

(S. R. Kraft*)

In a previous discussion of the MOS deep depletion method for profiling dopant density (NBS Spec. Publ. 400-17, pp. 8, 10-11), it was observed that the model for extracting the profile breaks down in the region near the surface due to the departure of the experimental capacitance-voltage curve from the ideal depletion curve. An analysis was carried out to determine how close to the surface one can make a profile measurement before the depletion model breaks down.

An experimental high frequency deep depletion curve, an ideal high frequency deep depletion curve, and a theoretical low frequency curve are illustrated in figure 14 for the case in which the flat band voltage occurs at zero applied gate voltage (i. e., work function differences, oxide charge, and interface state charge are neglected). Although a uniformly doped p-type substrate is assumed for purposes of illustration, the results are applicable to n-type substrates and can be extended to the case of nonuniform (with depth) dopant distributions.

The experimental deep depletion curve deviates from the ideal in the accumulation region, at the flat-band condition, and partly into the depletion region. However, in these regions,

NBS Mathematical Analysis Section, Applied

Mathematics Division

(9)

where N is the assumed constant dopant denA U is the Fermi potential, f

normalized to kT/q, where k is Boltzmann's constant, T is absolute temperature, and q is the electronic charge, and are referenced to the intrinsic Fermi potential.

In carrying out the analysis, eq (8) is solved iteratively to determine the surface potential which corresponds to the maximum permissible error in N(X). The value of X for this value of surface potential, calculated from eq (9), gives the minimum depth (X) which corresponds to the given error; `min' the profile is more accurate at larger values of X. It turns out that, for sufficiently extrinsic material (N, ≥ 1014 cm-3), the

A

A

ratio N(X)/N is essentially independent of N and that X is inversely proportional 'A' min to the square root of N

'A'

The results of this analysis are plotted in figure 15 which presents error curves for the minimum profiling depth as a function of the background dopant level. For example, with a background dopant density of 1016 cm-3, one can determine the profile with error approaching 1 percent for depths near 0.14 um; the

-1.0

1.0

2.0

Vg (VOLTS)

A

=

Capacitance-voltage characteristics of a p-type MOS capacitor with N 1015 cm -3 X = 120 nm, and C = 2.88 x 10-8 F/cm2. (Curve A, high frequency, deep depletion, experimental; Curve B, high frequency, deep depletion, ideal; Curve C, low frequency, theoretical.)

The MOS capacitance method for epitaxial layer thickness measurement was raised to a higher level of sophistication by employing the deep depletion MOS capacitance-voltage (C-V) method (NBS Spec. Publ. 400-17, pp. 8, 10-11). The method is basically the rampvoltage method as it has been described (NBS Spec. Publ. 400-4, p. 51) except that instead of merely locating the capacitance, Ct, at which a break in the C-V curve occurs, the entire dopant density profile is calculated from the C-V curve. Consequently, the deep depletion method is applicable over the wider range associated with the ramp-voltage method (NBS Spec. Publ. 400-17, pp. 39-41).

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04

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DISTANCE INTO SPECIMEN (μm)

Dopant density profiles calculated from the deep depletion C-V characteristics of an MOS capacitor on four epitaxial layers. (a, Wafer 2303, thermal oxide dielectric; b, Wafer 2353, thermal oxide dielectric; c, Wafer 2302, negative photoresist dielectric; d, Wafer 2351, negative photoresist dielectric. The vertical bar marks the layer thickness as measured by the step-relaxation method.)

Typical dopant density profiles are shown for devices on four wafers in figure 16. For three of the specimens, the epitaxial thickness was measured by the step-relaxation method (NBS Spec. Publ. 400-4, p. 51) and is indicated by a vertical line which, in each case, lies within the transition region which constitutes the layer-substrate interface. The fourth specimen was not measurable by the step-relaxation method for a voltage step from +100 V to -100 v. The high dopant density calculated for shallow depths is an artifact of the measurement (sec. 5.3) and does not represent a real dopant density variation.

In two of the wafers studied, the dielectric was thermally grown silicon dioxide; in the other two, the dielectric was negative photoresist (NBS Spec. Publ. 400-12, p. 26). In obtaining these profiles, a triangular voltage waveform was applied to the devices. The capacitance of the device for the positive-going voltage could therefore be observed in addition to the capacitance for negative-going voltage. For the wafers having thermal oxide dielectric the capacitance was nearly a single-valued function of voltage regardless of the voltage slope. For the wafers having negative photoresist dielectric, however, there was a significant dependence on the slope. With the negative photoresist dielectric there was also an additional anomaly in the C-V curve at shallow depths. Because of these effects, the profiles measured with oxide dielectric are believed to be more accurate than those measured with photoresist dielectric, but the problems do not appear to affect the determination of the epitaxial layer thickness.

the scatter for the case of no signal averaging (single response) is a result of the 10-bit resolution of the capacitance measurement and the manner in which the computer operates on arrays.

Examination of these profiles graphically illustrates the problem which has been encountered in attempting to correlate measurements of epitaxial layer thickness by different methods. The transition region has a finite width and different methods identify different points in the transition region as the location of the boundary between layer and substrate. Hence, the agreement between methods depends on the nature of the transition region, especially for the case of very thin layers where the width of the transition region may be comparable with the layer thickness. The present procedure may be of use in developing suitable criteria for definition of the location of the boundary or in controlling the profile shape in the transition region. (R. L. Mattis)

5.5. Bias-Temperature Stress Test

A preliminary set of measurements was carried out as the initial phase of an effort to develop improved understanding of the application of the bias-temperature stress test to the characterization of oxide films. The oxides used in this phase of the study were thermally grown on 2.0-in. (51-mm) diameter n-type silicon wafers with room temperature resistivity in the range 5 to 10 cm and <100> surfaces. Oxidation at 1000°C for 100 min in dry oxygen resulted in an oxide film approximately 80 nm thick. Following the oxidation the wafers were annealed in dry nitrogen at 1000°C for 20 min. Aluminum was e-beam evaporated over the oxide to a thickness of about 500 nm, further annealed in dry nitrogen at 500°C for 15 min, and patterned with the Metal mask of Test Pattern NBS-3 (NBS Spec. Publ. 400-12, pp. 19-22). The entire backside of the wafer was metallized with antimony-doped gold.

The test pattern mask contains four 15-mil (0.38-mm) diameter capacitor gate electrodes (test structures 3.2, 3.3, 3.8, and 3.19); the test pattern is repeated every 200 mils (5.1 mm) in both directions across the wafer. The primary measured quantity for the investigation is the flat-band voltage, V, of FB' MOS capacitors determined by the high frequency capacitance-voltage (C-V) technique (NBS Spec. Publ. 400-4, pp. 34-37). The general procedure for the study of a given

Each

Six lots of several slices each have been fabricated by the processing facility with no special treatment of the furnace. As an example of preliminary results, figure 18 summarizes the flat-band voltage measurements on the four wafers of the fifth lot. bar represents the span of the flat-band voltages for the measured number of devices shown in parentheses and is labeled with the condition of the device. To begin with, the flat-band voltages of the as-processed wafers fell in the region from -0.21 to -0.27 V. Three of the four wafers had flat-band voltages for the 16 measured devices tightly grouped within ±10 mV; these were subjected to additional study. It should be noted here that since the gate metal is aluminum, the intrinsic shift of the flat-band voltage due to the metal-semiconductor contact potential difference is about -0.3 V [40] for the specimens studied. Therefore, in the as-processed condition, these devices appear to have a net negative charge in the interface or oxide region of the capacitors.

Wafer 5A was subjected to negative BT stress, positive BT stress, and heat treatment. The