National Bureau of Standards Special Publication 400-34
Nat. Bur. Stand. (U.S.), Spec Publ. 400-34, 57 pages (Dec. 1976)

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2

is a schematic illustration of a typical plot of normal-

ized capacitance C versus voltage

N

PAGE

Figure 2.

Figure 3.

Figure 4.

Isolation box arrangement for measuring C(V) with an
applied bias voltage larger than the C-meter limit:
(a) block diagram, and (b) isolation box circuit

Simplified version of C-meter bias-protection circuits:
(a) normal operating mode, and (b) after a capacitor
sample breaks down with a large bias voltage applied
to it..

3

5

Schematic circuit diagram of C-meter bias-isolation
unit

7

Figure 5.

Plots of relative sensitivity factor S (Cs) and rel-
ative incremental sensitivity factor S' (Cs) versus
Cs with series resistance R as a parameter

12

Figure 6.

(a) Schematic representation of the experimental
arrangement for testing the transient suppression cap-
ability of the BIU. (b) Photograph of a typical
observed transient (HI terminal to ground) .

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Figure 7.

Calibration curves for BIU operating with BEC Model
71A C-meter

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Figure 8.

Calibration curves for BIU operating with BEC Model
72AD C-meter

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Figure 9.

Calibration curves for BIU operating with PAR Model
410 C-meter .

20

Figure Ml

Figure M2

Front panel Capacitance-Meter Bias-Isolation Unit . . .
Side panels

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30

Figure M10 Peaker/zero-suppression acrylic mounting bracket

Zero-suppression fine capacitor acrylic mounting
bracket.

37

37

37

Figure M11

39

Figure Al

Front view of Capacitance-Meter Bias-Isolation Unit

45

Figure A2

Top view with top cover removed Figure A3 Top view of Peaker/Zero Suppression circuit with top cover and shield cover removed

Table 1.

LIST OF TABLES

Electrical Parts List for Capacitance-Meter Bias-Isolation
Unit

Table 2.

Test-Signal Spectral Analysis for Three C-Meters

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26

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PREFACE

This study was carried out at the RCA Laboratories as a part of the Semiconductor Technology Program in the Electronic Technology Division at the National Bureau of Standards. The Semiconductor Technology Program serves to focus NBS efforts to enhance the performance, interchangeability, and reliability of discrete semiconductor devices and integrated circuits through improvements in measurement technology for use in specifying materials and devices in national and international commerce and for use by industry in controlling device fabrication processes. The work was supported by the Defense Advanced Research Projects Agency* through the National Bureau of Standards' Semiconductor Technology Program, Contract 5-35912. The contract was monitored by R. L. Raybold as the Contracting Officer's Technical Representative (COTR) and R. Y. Koyama as Assistant COTR.

Certain commercial equipment, instruments, or materials are identified in this report in order to adequately specify the experimental procedure. In no case does such identification imply recommendation or endorsement by the National Bureau of Standards, nor does it imply that the material or equipment identified is necessarily the best available for the purpose.

Larger scale drawings of the mechanical parts are available on request from the COTR, TECH-A-361, National Bureau of Standards, Washington, DC 20234.

*Through ARPA Order 2397, Program Code 6D10.