30x10 28 26 24 22 20 18 16 14 12 10 8 T Plot of current vs time for bare silicon wafer and silicon Figure 25. APPLIED VOLTAGE (V) Plot of charge transported vs applied voltage for silicon dioxide-coated wafer. The suspension is the same as for figure 24. Sulfonate content was 0.1% to C2C13F3 by volume for the points and 0.2% for the points. Figure 26. CHARGING AGENT CONTENT IN 250 cc C2 Cl3 F3 (cc) Plot of glass deposited on silicon dioxide-coated wafers as function of concentration of petroleum barium sulfonate. develop. The addition of acetone results in qualitatively the same behavior. 4.3.6 Summary It has been possible to obtain useful decoration of defects in insulating passivation layers on device wafers by deposition of particles such as glass or phosphor (zinc silicate) from insulating liquids by a conventional cell electrophoretic technique. The use of conducting liquids involves adhesion problems with the decorating particles, and the possibility of destructive breakdown because of the low impedance of the system. The contrast ratio of the process can be optimized by the addition of conductivity-increasing agents. At best, however, the defect detectability, ease of observation, and contrast ratio are inferior to the methods described in the next section. In this section the decoration method of electrostatic charging of the sample followed by immersion in an insulating liquid containing charged decorating particles is described. Basic principles of the processes have been discussed [7]. In the first step, ions from an atmospheric pressure glow discharge (corona) are deposited on the insulating regions of the sample. Then the sample is immersed in a suspension of charged particles. Depending on the relative signs of the charged particles and the deposited surface ions, the charged particles are attracted to the charged insulating regions, resulting in reverse decoration, or to the defects, resulting in direct decoration. 4.4.1 Corona-Charging Process The first step for either direct or reverse decoration is the deposition of ions on the insulating regions of the sample as shown in figure 27. 4.4.1.1 Equipment - The source of ions deposited on the sample is a plane array of 40-μm-diameter nickel alloy wires. This wire grid consists of seven parallel wires 1.8 cm apart, held in an acrylic frame in a horizontal plane. The wires are commonly connected to a highvoltage dc power supply capable of +10,000 V and 6 mA. It is recommended that only rf-type dc power supplies with current limitation of no more than 10 mA be used for operator safety. A grounded plate is placed 3 cm above the wires to provide greater current uniformity and to protect the wires from mechanical damage. The sample is placed on grounded plate about 2 cm below the wire array. The power supply is operated from a foot switch. The process is carried out at relative humidity below 30% in a glove box in flowing nitrogen. 4.4.1.2 Parameter Study of Charging In order to understand the surface charge deposition process on device wafers, measurements of surface voltage of charged wafers were done as functions of sample geometry, passivating layer thickness, corona voltage, relative |